1. Field of the Invention
The present invention relates to an apparatus and a method for driving a plasma display panel (PDP), and more particularly, to an apparatus and a method for driving a PDP that automatically controls power using a compensated average signal level to minimize differences between power consumption of red, green, and blue discharge cells.
2. Discussion of the Related Art
FIG. 1 is a perspective view showing a structure of a typical three-electrode surface discharging type PDP.
Referring to FIG. 1, the PDP 1 includes a front glass substrate 10 and a rear glass substrate 13. Address electrodes AR1, AG1, . . . , AGm, ABm, dielectric layers 11 and 15, Y electrode lines Y1, . . . , Yn, X electrode lines X1, . . . , Xn, a phosphor layer 16, a barrier rib 17, and an MgO protective layer 12 are disposed between the front and rear glass substrates 10 and 13.
The address electrode lines AR1, AG1, . . . , AGm, ABm are formed on the rear glass substrate 13, and the lower dielectric layer 15 covers them. The barrier ribs 17 are formed on the lower dielectric layer 15 in between, and in parallel to, the address electrode lines AR1, AG1, . . . , AGm, ABm, and they divide a discharging region of each display cell and prevent optical cross talk between cells. The phosphor layer 16 is formed on the lower dielectric layer 15 and on the sides of the barrier ribs 17.
The X electrode lines X1, . . . , Xn and the Y electrode lines Y1, . . . , Yn are formed orthogonally to the address electrode lines AR1, AG1, . . . , AGm, ABm on a lower surface of the front glass substrate 10. Crossing points of a pair of X and Y electrodes and an address electrode form display cells. The upper dielectric layer 11 covers the X electrode lines X1, . . . , Xn and the Y electrode lines Y1, . . . , Yn. The protective layer 12, which is typically made of a MgO layer, protects the PDP 1 from a strong electric field. It is formed on, and covers, the upper dielectric layer 11. A plasma forming gas is filled in the discharge space 14.
U.S. Pat. No. 5,541,618 discloses an address-display separation (ADS) driving method that is often used as the driving method of a typical PDP.
FIG. 2 is a block diagram showing a driving apparatus 2 of the PDP shown in FIG. 1.
Referring to FIG. 2, the driving apparatus 2 includes an image processor 26, a logic controller 22, an address driver 23, an X driver 24, and a Y driver 25. The image processor 26 converts external analog image signal into internal image signals, such as 8 bit red (R), green (G), and blue (B) image data, clock signals, and vertical and horizontal synchronization signals. The logic controller 22 generates driving control signals SA, SY, and SX according to the internal image signals from the image processor 26.
Here, the address driver 23, the X driver 24, and the Y driver 25 receive the driving control signals SA, SY, and SX, generate the driving signals, and apply the generated driving signals to the electrode lines.
FIG. 3 is a timing view showing a typical ADS driving method of the PDP shown in FIG. 1.
Referring to FIG. 3, a unit frame is divided into 8 sub-fields SF1, . . . , SF8 for time division gray scale display. Each sub-field SF1˜SF8 may be divided into a reset period R1, . . . , R8, an address period A1˜A8, and a sustain period S1˜S8.
PDP brightness is in proportion to lengths of the sustain periods S1˜S8 in the unit frame, and the length of the sustain periods S1˜S8 in the unit frame is 255 T (T denotes a unit time). Time corresponding to 2n-1 may be set for the sustain period Sn in nth sub-filed SFn. Accordingly, by selecting appropriate sub-fields, 256 gray levels, including 0 gray level, may be displayed.
FIG. 4 is a timing view showing typical driving signals applied to the electrode lines of the PDP shown in FIG. 1 in the unit sub-field SFn of FIG. 3.
Referring to FIG. 4, SAR1, . . . , SABm denote the driving signals applied to the address electrode lines (AR1, AB1, . . . , AGm, ABm of FIG. 1), SX1, . . . SXn denote the driving signals applied to the X electrode lines (X1, . . . , Xn in FIG. 1), and SY1, . . . , SYn denote the driving signals applied to the Y electrode lines (Y1, . . . , Yn in FIG. 1).
Referring to FIG. 4, in the reset period PR of the unit sub-field, a voltage applied to the X-electrode lines X1, . . . , Xn rises from a ground voltage VG to a first voltage Ve. During this time, ground voltages VG are applied to the Y-electrode lines Y1, . . . , Yn and the address electrode lines AR1, . . . , ABm.
Then, a voltage applied to the Y-electrode lines Y1, . . . , Yn rises from the second voltage VS, to the voltage (VSET+VS). During this time, the ground voltages VG are applied to the X-electrode lines X1, . . . , Xn and the address electrode lines AR1, . . . , ABm.
Next, with the voltage of Ve applied to the X-electrode lines X1, . . . , Xn, the voltage applied to the Y-electrode lines Y1, . . . , Yn falls from the second voltage VS to the ground voltage VG. During this time, the ground voltage VG is applied to the address electrode lines AR1, . . . , ABm.
In the following address period PA, display data signals are applied to the address electrode lines, and scan signals of ground voltages VG are sequentially applied to the Y-electrode lines Y1, . . . , Yn, which are biased to be fourth voltages (VSCAN). The first voltage Ve is applied to the X-electrode lines X1, . . . , Xn during the address period PA.
In the following sustain period PS, sustain discharge pulses of the second voltage VS are alternately applied to the Y-electrode lines Y1, . . . , Yn and the X-electrode lines X1, . . . , Xn to display images on the discharging cells that were selected during the previous address period (PA).
FIG. 5 is a graph showing general automatic power control (APC) principles that may be utilized in driving a PDP.
Referring to FIG. 5, according to the general APC method, the number of discharge cells that are turned on among all discharge cells on the panel controls the number of sustain pulses that are applied in the sustain period of one unit frame. The number of sustain pulses at the unit frame is in inverse-proportion to the load ratio. That is, if the load ratio is small, the number of sustain pulses in the unit frame increases, thus improving the brightness of the displayed image, and if the load ratio is high, the number of sustain pulses at the unit frame decreases, thus reducing power consumption.
On the other hand, an average signal level (ASL) is an average of all signal levels applied to the discharge cells for displaying gray level per frame. Thus the average signal level has the same meaning as load ratio, but a unit of the average signal level differs from a unit of the load ratio. Hence, “load ratio” and “average signal level” may be used interchangeably herein. The ASL of the unit frame may be calculated by dividing an accumulated signal level of all discharge cells forming the panel by the number of entire discharge cells. The discharge cells may display R, G and B colors.
R, G, and B discharge cells with the same ASLs may have different power consumption due to various elements such as asymmetric cell structure. Thus, power consumption may differ by gray level when driving a PDP according to the APC method.
That is, in cases of full red, full green, and full blue colors, the power consumption of the R, G, and B discharge cells may differ even though they have the same ASLs. Thus, desired power consumption may not be obtained according to the conventional APC method.
FIG. 6 and FIG. 7 show power consumption with respect to the red, green, and blue colors in an asymmetric panel according to the conventional APC driving method.
FIG. 6 and FIG. 7 show cases where the red, green, and blue colors are displayed while the load ratio is increased from 0% to 100% by 10% according to the conventional APC method. As these figures show, power consumption may be different according to the displayed colors even with the same load ratios.